and subtraction • Logic operations: AND and OR • Displaying results: – For addition and

1Functional Specifications Design a Verilog program that performs the basic arithmetic and logic operations (ALU) on two 3-bit binary inputs, and displays the outcome on 7-segments. • Arithmetic operations: addition and subtraction • Logic operations: AND and OR • Displaying results: – For addition and subtraction: display the result using decimal digits – For logic AND and OR: display the result using binary digits 2 Objectives Demonstrate the ability to 1. program in Verilog to describe digital logic circuit on behavioral and gate level; 2. use Xilinx ISE for coding and synthesizing the logic design; 3. use Spartan 3 development board to implement and verify the design. i want like this cods  to use in the this is Example module seg7(bcd, leds, control, enable); input [3:0] bcd; input [1:0] control; output reg [1:7] leds; output reg [3:0] enable; always @ (control) case (control) 2’b00: enable = 4’b1110; 2’b01: enable = 4’b1101; 2’b10: enable = 4’b1011; 2’b11: enable = 4’b0111; endcase always @ (bcd) case (bcd) 4’b0000: leds = 7’b0000001; 4’b0001: leds = 7’b1001111; 4’b0010: leds = 7’b0010010; 4’b0011: leds = 7’b0000110; 4’b0100: leds = 7’b1001100; 4’b0101: leds = 7’b0100100; 4’b0110: leds = 7’b0100000; 4’b0111: leds = 7’b0001111; 4’b1000: leds = 7’b0000000; 4’b1001: leds = 7’b0000100; 4’b1010: leds = 7’b0001000; 4’b1011: leds = 7’b1100000; 4’b1100: leds = 7’b0110001; 4’b1101: leds = 7’b1000010; 4’b1110: leds = 7’b0010000; 4’b1111: leds = 7’b0111000; default: leds = 7’bx; endcase endmodule